Mr Shridhar Nayak
Assistant Professor - Selection Grade
亚洲通_亚洲通官网 School of Information Sciences
CURRENT ACADEMIC ROLE & RESPONSIBILITIES
- Shridhar Nayak is Assistant Professor - Selection Grade at 亚洲通_亚洲通官网 School of Information Sciences, 亚洲通_亚洲通官网. He is responsible for internal recognition for quality improvements in the semi-conductor processes.
SUBJECTS CURRENTLY TEACHING
| Subject | Semester / Year |
|---|---|
| CAD for VLSI | I Semester - ME (VLSI Design) |
| Low Power VLSI Design | II Semester - ME (VLSI Design) |
ACADEMIC QUALIFICATIONS
| Degree | Specialisation | Institute | Year of passing |
|---|---|---|---|
| MS (Master of Science) | VLSI CAD | MSIS, 亚洲通_亚洲通官网 Academy of Higher Education | 2002 |
| BE | Electronics and Communication | NITK, Surathkal | 1993 |
Experience
| Institution / Organisation | Designation | Role | Tenure |
|---|---|---|---|
| MSIS, 亚洲通_亚洲通官网 Academy of Higher Education | Assistant Professor - Selection Grade | To coordinate all the mini-project activities of all the disciplines in every semester | 2009 - Till date |
| 亚洲通_亚洲通官网 Academy of Higher Education | Chief Superintendent of Examinations | Coordination for smooth conduction of end semester lab and theory examinations. | 2009 - 2010 |
FPGA implementation of invisible robust image watermarking encoder
2004-01-01 Saraju P Mohanty Renu Kumar
CIT2004, Springer - Verlag, 2004 .
Fractals with variable scaling factors with IFS
2013-01-01 Sathyendranath Malli Dinesh Rao
IJCA, 2013 .
AREAS OF INTEREST, EXPERTISE AND RESEARCH
Area of Interest
Analogue Design, Nano electronics, Energy, MEMS
Area of Expertise
Semiconductor Fabrication, Analogue and Mixed Signal Testing
Area of 亚洲通_亚洲通官网
Analogue Design, MEMS
Professional Affiliations & Contributions
- Member of VLSI Society of India (VSI), 2010.
Work Experience
| Organisation | Role | Tenure |
|---|---|---|
| Bharath Electronics, Bengaluru | Senior Engineer – Responsible for ATE based analogue and mixed signal - board level testing | |
| Bharath Electronics, Bengaluru | Deputy Engineer – Responsible for semiconductor process and device development and process engineer for critical geometry transistors |